The inherent queuing delay of parallel packet switches

David Hay, Hagit Attiya
IEEE Transactions on Parallel and Distributed Systems,
Switch and router design


The parallel packet switch (PPS) extends the inverse multiplexing architecture and is widely used as the core of contemporary commercial switches. This paper investigates the inherent queuing delay introduced by the PPS’s demultiplexing algorithm, responsible for dispatching cells to the middle-stage switches, relative to an optimal work-conserving switch. We first consider an N times N PPS without buffers in its input ports, operating at external rate R, internal rate r < R, and speedup (or overcapacity) S. We show that the inherent queuing delay of a symmetric and fault-tolerant PPS, where every demultiplexer may dispatch cells to all middle-stage switches, is Ω(N R/r) if no information is shared between the input ports. Sharing information between the input ports significantly reduces this lower bound, even if the information is outdated. These lower bounds indicate that employing algorithms using slightly out-of-date information may greatly improve the PPS performance. When the PPS has buffers in its input ports, an Ω(N/S) lower bound holds if the demultiplexing algorithm uses only local information or the input buffers are small relative to the time an input port needs to learn the switch global information.

  author={Attiya, H. and Hay, D.},
  journal={IEEE Transactions on Parallel and Distributed Systems}, 
  title={The Inherent Queuing Delay of Parallel Packet Switches},